LLVM Chapter 9 reduction

64-by-32 unsigned divide from hi:lo pair

File: udiv_hilo32_x86.ll

Issue:

LLVM does not reduce a (zext hi << 32) | zext lo divided by zext d into the natural x86 %edx:%eax / r32 form, even with an explicit llvm.assume(hi < d) proving the quotient fits in 32 bits.
Current llc emits divq.

Observed current-head code:

udiv_hi_lo:
  movl  %esi, %eax
  shlq  $32, %rdi
  orq   %rdi, %rax
  movl  %edx, %ecx
  xorl  %edx, %edx
  divq  %rcx
  retq

Expected x86_64 shape:

movl  %edi, %edx
movl  %esi, %eax
divl  %ecx
retq

Suggested bug report title:

llc x86_64 misses divl EDX:EAX idiom for (zext hi << 32 | zext lo) udiv zext d with assume(hi < d)