Architectural Issues

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Problems

2.1

A SPARC program contains these instructions. (These aren’t intended as a useful program, just as some instruction format examples.)

Loc  Hex         Symbolic
1000 40 00 03 00 CALL X
1004 01 00 00 00 NOP; no operation, for delay
1008 7F FF FE ED CALL Y
100C 01 00 00 00 NOP
1010 40 00 00 02 CALL Z
1014 01 00 00 00 NOP
1018 03 37 AB 6F SETHI r1,3648367 ; set high 22 bits of r1
101C 82 10 62 EF ORI r1,r1,751; OR in low 10 bits of r1

1a. In a CALL instruction the high two bits are the instruction code, and the low 30 bits a signed word (not byte) offset. What are the hex addresses for X, Y, and Z?

1b. What does the call to Z at location 1010 accomplish?

1c. The two instructions at 1018 and 101C load a 32 bit address into register 1. The SETHI loads the low 22 bits of the instruction into the high 22 bits of the register, and the ORI logically or’s the low 13 bits of the instruction into the register. What address will register 1 contain?

1d. If the linker moves X to be at location 2504(hex) but doesn’t change the location of the code in the example, to what will it change the instruction at location 1000 so it still refers to X?

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2.2

A Pentium program contains these instructions. Don’t forget that the x86 is little-endian.

Loc  Hex             Symbolic
1000 E8 12 34 00 00  CALL A
1005 E8 ?? ?? ?? ??  CALL B
100A A1 12 34 00 00  MOV %EAX,P
100F 03 05 ?? ?? ?? ?? ADD %EAX,Q

2a. At what location are routine A and data word P located? (Tip: On the x86, relative addresses are computed relative to the byte address after the instruction.)

2b. If routine B is located at address 0F00 and data word Q is located at address 3456, what are the byte values of the ?? bytes in the example?

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2.3

Does a linker or loader need to “understand” every instruction in the target architecture’s instruction set? If a new model of the target adds new instructions, will the linker need to be changed to support them? What if it adds new addressing modes to existing instructions, like the 386 did relative to the 286?

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2.4

Back in the Golden Age of computing, when programmers worked in the middle of the night because that was the only time they could get computer time, rather than because that’s when they woke up, many computers used word rather than byte addresses. The PDP-6 and 10, for example had 36 bit words and 18 bit addressing, with each instruction being a word with the operand address in the low half of the word. (Programs could also store addresses in the high half of a data word, although there was no direct instruction set support for that.) How different is linking for a word-addressed architecture compared to linking for a byte addressed architecture?

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2.5

How hard would it be to build a retargetable linker, that is, one that could be built to handle different target architectures by changing a few specific parts of the source code for the linker? How about a multi-target linker, that could handle code for a variety of different architectures (although not in the same linker job)?